A memory or any memory mapped I/O device, such as a printer, a display, a port, or a register is referred to herein as a “memory device.” One or more memory devices may be coupled to an N-bit address bus, which can be used to address the memory devices directly. Direct addressing with an N-bit address bus requires that the address space comprise no more than 2N addresses. For example, a typical 8-bit address bus can be used to directly address 28 or 256 locations or addresses in a memory device.
Frequently, more than one memory device is coupled to the bus. Further, the address space not only includes addresses which identify locations in memory, but also addressable locations within other memory devices coupled to the bus. Continuing with the 8-bit address bus example, 200 of the 256 locations may be random access memory locations of a memory chip, with the remaining 56 addresses being used to identify registers or ports in other memory devices. Most memory chips, however, have a capacity that is greater than 256 locations, and most systems have a memory space that is greater than 256. For this reason, a wider address bus is often used. For example, a 16 bit bus can be used to access any location within a memory space of 216 or 65,536 (“64K”) directly. As another example, the address bus in personal computers today is commonly 36 bits, allowing any location in a 64 GB (236) address space to be addressed directly.
Many systems today are much less complex than a personal computer, however, and many still use a relatively small bus, such as an 8-bit bus. Further, such systems may have only a single bus, used for communicating both address and data. Reasons for the use of a single, relatively small bus include cost and power savings. Hand-held devices, battery-powered portable devices, cellular telephones, and embedded systems are examples of systems that commonly employ a single 8-bit bus. Even though such systems use an 8-bit bus, it is desirable to have an address space greater than 256 addresses in such systems. A technique can be used to access all of the locations in a system having an 8-bit bus even though the address space is greater than 256 addresses. This technique is known as “indirect addressing.”The indirect addressing technique permits any location in a memory space having 2M locations to be addressed using an N-bit bus, where M is greater than N. With the indirect addressing technique, the first step is to transmit N bits of address (“address R1”) over the N-bit bus. The address R1 is used to identify a first register. Second, N bits of data (“Data 1”) are transmitted over the bus and stored in a register. The register where Data 1 is stored is specified by address R1, that is, Data 1 is stored in the first register. The N bits of data, Data 1, define one byte.
The foregoing steps are repeated for a second byte. A second N bits of address (“address R2”) are transmitted over the bus. The address R2 is used to identify a second register. A second N bits of data (“Data 2”) are transmitted over the bus and stored in the register specified by address R2, that is, in the second register. The N bits of data, Data 2, define a second byte.
Two bytes of data (Data 1 and Data 2) are now stored in the first and second registers. The indirect addressing technique uses these two bytes to define an address in the system's 2M-bit memory space, an address which is two bytes (N+N bits) in length. The two bytes in the first and second registers are combined to define a complete address for addressing one of the 2M memory locations in the memory space. Since the two bytes of “data” stored in the first and second register are used to define an address, they may also be referred to herein as “address-data bytes.”
As described above, the prior art indirect addressing technique requires the transmission over the bus of at least two register addresses and at least two address-data bytes. With regard to references herein to the prior art indirect addressing technique, the phrases “address cycle” and “data cycle,” are intended to refer, respectively, to the activities associated with transmitting a register or “data port” address, and the activities associated with transmitting a byte of address-data or other data. In the above example, using this terminology, two address cycles and two data cycles are required. Control signals, such as Address Enable and Write Enable, are conventionally used to define address and data cycles. With regard to the description of the preferred embodiments of the invention herein, the phrases “address cycle” and “data cycle” are intended to refer the activities there described.
After the two address-data bytes have been stored in the registers R1, R2, the CPU may perform either a read operation or a write operation, and the memory device uses the address-data bytes stored in the registers R1, R2 to perform the read/write operation. For example, a CPU can transmit a 16 bit address to a memory device using an 8-bit data bus by first transmitting an upper (or lower) address-data byte to the memory device during a first address cycle and a first data cycle, and then transmitting a lower (or upper) address-data byte during a second address cycle and a second data cycle. The CPU then transmits a data port address in an address cycle, and either writes data to or reads data from the location specified by the address in registers R1, R2 in a data cycle.
Using the indirect addressing technique to address a location in a memory space having 2M addresses using an N-bit bus requires at least two, and maybe more, sets of address and data cycles. Further, to access a memory location after it has been addressed, requires an additional address cycle and data cycle. In general, as the size of the 2M address memory space increases, that is, when M increases while N remains constant, more address and data cycles are required to indirectly address the memory space using the N-bit bus. In addition, for each new address, all of the aforementioned steps must be repeated. These constraints undesirably limit the speed of communication between the CPU and the memory. Accordingly, there is a need for a method and apparatus for high speed addressing of a memory space from a relatively small address space providing for faster communication with a memory device than has been available in the prior art.